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| M48T86 5V PC REAL TIME CLOCK s DROP-IN REPLACEMENT for PC COMPUTER CLOCK/CALENDAR COUNTS SECONDS, MINUTES, HOURS, DAYS, DAY of the WEEK, DATE, MONTH and YEAR with LEAP YEAR COMPENSATION INTERFACED WITH SOFTWARE AS 128 RAM LOCATIONS: - 14 Bytes of Clock and Control Registers - 114 Bytes of General Purpose RAM 28 s SNAPHAT (SH) Battery/Crystal s 24 1 s s SELECTABLE BUS TIMING (Intel/Motorola) THREE INTERRUPTS are SEPARATELY SOFTWARE-MASKABLE and TESTABLE - Time-of-Day Alarm (Once/Second to Once/Day) - Periodic Rates from 122s to 500ms - End-of-Clock Update Cycle 1 SOH28 (MH) PCDIP24 (PC) Battery/Crystal CAPHAT Figure 1. Logic Diagram s s PROGRAMMABLE SQUARE WAVE OUTPUT SELF-CONTAINED BATTERY and CRYSTAL in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT(R) TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP CONTAINS the BATTERY and CRYSTAL PIN and FUNCTION COMPATIBLE with bq3285/7A and DS128887 AD0-AD7 E R/W DS AS RST RCL MOT M48T86 SQW IRQ s VCC 8 s s VSS AI01640 May 2000 1/23 M48T86 Figure 2. DIP Connections Figure 3. SOIC Connections MOT NC NC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS 24 1 23 2 22 3 21 4 20 5 19 6 M48T86 18 7 17 8 16 9 15 10 11 14 12 13 AI01641 VCC SQW NC RCL NC IRQ RST DS NC R/W AS E NC MOT NC NC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS VSS 1 28 27 2 3 26 4 25 24 5 23 6 22 7 M48T86 21 8 20 9 19 10 18 11 17 12 16 13 15 14 AI01642 NC VCC SQW NC RCL NC IRQ RST DS NC R/W AS E NC Table 1. Signal Names AD0-AD7 E R/W DS AS RST RCL MOT SQW IRQ VCC VSS NC Multiplexed Address/Data Bus Chip Enable Input Write Enable Input Data Strobe Input Address Strobe Input Reset Input RAM Clear Input Bus Type Select Input Square Wave Output Interrupt Request Output Supply Voltage Ground Not Connected Internally DESCRIPTION The M48T86 is an industry standard real time clock (RTC).The M48T86 is composed of a lithium energy source, quartz crystal, write-protection circuitry, and a 128 byte RAM array. This provides the user with a complete subsystem packaged in either a 24-pin DIP CAPHAT or 28-pin SNAPHAT SOIC. Functions available to the user include a non-volatile time-of-day clock, alarm interrupts, a one-hundred-year clock with programmable interrupts, square wave output, and 128 bytes of nonvolatile static RAM. The 24 pin 600mil DIP CAPHATTM houses the M48T86 silicon with a quartz crystal and a long life lithium button cell in a single package. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. 2/23 M48T86 Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG TSLD (2) Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Power Dissipation Value 0 to 70 -40 to 85 260 -0.3 to 7.0 -0.3 to 7.0 1 Unit C C C V V W VIO VCC PD Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. For the 28 lead SOIC, the battery/crystal package part number is "M4T28-BR12SH1". Automatic deselection of the device provides insurance that data integrity is not compromised should V CC fall below specified Power-fail Deselect Voltage (V PFD) levels. The automatic deselection of the device remains in effect upon power up for a period of 200ms (max) after V CC rises above VPFD, provided that the Real Time Clock is running and the count down chain is not reset. This allows sufficient time for V CC to stabilize and gives the system clock a wake up period so that a valid system reset can be established. The block diagram in Figure 3 shows the pin connections and the major internal functions of the M48T86. SIGNAL DESCRIPTION VCC, VSS. DC power is provided to the device on these pins.The M48T86 utilizes a 5V VCC. SQW (Square Wave Output). During normal operation (i.e. valid VCC), the SQW pin can output a signal from one of 13 taps.The frequency of the SQW pin can be changed by programming Register A as shown in Table 10. The SQW signal can be turned on and off using the SQWE bit (Register B; bit 3). The SQW signal is not available when VCC is less than VPFD. AD0-AD7 (Multiplexed Bi-Directional Address/ Data Bus). The M48T86 provides a multiplexed bus in which address and data information share the same signal path. The bus cycle consists of two stages; first the address is latched, followed by the data. Address/Data multiplexing does not slow the access time of the M48T86, since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS, at which time the M48T86 latches the address present on AD0AD7. Valid write data must be present and held stable during the latter portion of the R/W pulse. In a read cycle, the M48T86 outputs 8 bits of data during the latter portion of the DS pulse. The read cycle is terminated and the bus returns to a high impedance state upon a high transition on R/W. AS (Address Strobe Input). A positive going pulse on the Address Strobe (AS) input serves to demultiplex the bus. The falling edge of AS causes the address present on AD0-AD7 to be latched within the M48T86. MOT (Mode Select). The MOT pin offers the flexibility to choose between two bus types. When connected to VCC, Motorola bus timing is selected. When connected to V SS or left disconnected, Intel bus timing is selected. The pin has an internal pulldown resistance of approximately 20K ohms. 3/23 M48T86 Figure 4. Block Diagram OSCILLATOR /8 / 64 / 64 E VCC VBAT POWER SWITCH AND WRITE PROTECT VCC POK PERIODIC INTERRUPT/SQUARE WAVE SELECTOR SQUARE WAVE OUTPUT SQW IRQ RST REGISTERS A,B,C,D CLOCK/ CALENDAR UPDATE CLOCK CALENDAR, AND ALARM RAM DOUBLE BUFFERED DS R/W AS BUS INTERFACE BCD/BINARY INCREMENT STORAGE REGISTERS (114 BYTES) RCL AD0-AD7 AI01643 DS (Data Strobe Input). The DS pin is also referred to as Read (RD). A falling edge transition on the Data Strobe (DS) input enables the output during a a read cycle. This is very similar to an Output Enable (G) signal on other memory devices. E (Chip Enable Input). The Chip Enable pin must be asserted low for a bus cycle in the M48T86 to be accessed. Bus cycles which take place without asserting E will latch the addresses present, but no data access will occur. IRQ (Interrupt Request Output). The IRQ pin is an open drain output that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. IRQ returns to a high impedance state whenever Register C is read. The RST pin can also be used to clear pending interrupts. Because the IRQ bus is an open drain output, it requires an external pull-up resistor to V CC. 4/23 M48T86 RST (Reset Input). The M48T86 is reset when the RST input is pulled low. With a valid VCC applied and a low on RST, the following events occur: 1. Periodic Interrupt Enable (PIE) bit is cleared to a zero. (Register B; Bit 6) 2. Alarm Interrupt Enable (AIE) bit is cleared to a zero.(Register B; bit 5) 3. Update Ended Interrupt Request (UF) bit is cleared to a zero. (Register C; Bit 4) 4. Interrupt Request (IRQF) bit is cleared to a zero. (Register C Bit 7) 5. Periodic Interrupt Flag (PF) bit is cleared to a zero. (Register C; Bit 6) 6. The device is not accessible until RST is returned high. 7. Alarm Interrupt Flag (AF) bit is cleared to a zero. (Register C; Bit 5) 8. The IRQ pin is in the high impedance state. 9. Square Wave Output Enable (SQWE) bit is cleared to zero. (Register B; Bit 3). 10.Update Ended Interrupt Enable (UIE) is cleared to a zero. (Register B; Bit 4) RCL (RAM Clear). The RCL pin is used to clear all 114 storage bytes, excluding clock and control registers, of the array to FF(hex) value. The array will be cleared when the RCL pin is held low for at least 100ms with the oscillator running. Usage of this pin does not affect battery load. This function is applicable only when V CC is applied. R/W (Read/Write Input). The R/W pin is utilized to latch data into the M48T86 and provides functionality similar to W in other memory systems. ADDRESS MAP The address map of the M48T86 is shown in Figure 9. It consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar and alarm data, and 4 bytes which are used for control and status. All bytes can be read or written to except for the following: 1. Registers C & D are read-only. 2. Bit 7 of Register A is read-only. The contents of the four Registers A, B, C, and D are described in the "Registers" section. 5/23 M48T86 Table 3. Time, Calendar and Alarm Formats Range Address 0 1 2 3 RTC Bytes Decimal Seconds Seconds Alarm Minutes Minutes Alarm Hours, 12-hrs 4 Hours, 24-hrs Hours Alarm, 12-hrs 5 Hours Alarm, 24-hrs 6 7 8 9 Day of Week (1 = Sun) Day of Month Month Year 0-23 1-7 1-31 1-12 0-99 0-23 1-12 0-59 0-59 0-59 0-59 1-12 Binary 00-3B 00-3B 00-3B 00-3B 01-0C AM 81-8C PM 00-17 01-0C AM 81-8C PM 00-17 01-07 01-1F 01-0C 00-63 BCD 00-59 00-59 00-59 00-59 01-12 AM 81-92 PM 00-23 01-12 AM 81-92 PM 00-23 01-07 01-31 01-12 00-99 TIME, CALENDAR, AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar, and alarm registers are set or initialized by writing the appropriate RAM bytes. The contents of the time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm register, the SET bit (Register B; Bit 7) should be written to a logic "1". This will prevent updates from occurring while access is being attempted. In addition to writing the time, calendar, and alarm registers in a selected format (binary or BCD), the Data Mode (DM) bit (Register B; Bit 2), must be set to the appropriate logic level ("1" signifies binary data; "0" signifies Binary Coded Decimal (BCD data). All time, calendar, and alarm bytes must use the same data mode. The SET bit should be cleared after the Data Mode bit has been written to allow the Real Time Clock to update the time and calendar bytes. Once initialized, the Real Time Clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the ten data bytes. Table 3 shows the binary and BCD formats of the time, calendar, and alarm locations. The 24/12 bit (Register B; Bit 1) cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, a logic one in the high order bit of the hours byte represents PM. The time, calendar, and alarm bytes are always accessible because they are double buffered. Once per second the ten bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. However, the probability of reading incorrect time and calendar data is low. Methods of avoiding possible incorrect time and calendar reads are reviewed later in this text. NON-VOLATILE RAM The 114 general purpose non-volatile RAM bytes are not dedicated to any special function within the M48T86. They can be used by the processor program as non-volatile memory and are fully accessible during the update cycle. 6/23 M48T86 Figure 5. AC Testing Load Circuit 5V Figure 6. AC Testing Load Circuit 5V 960 FOR ALL OUTPUTS EXCEPT IRQ 510 50pF 1.15k IRQ 130pF AI01644 AI01645 Table 4. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Note that Output Hi-Z is defined as the point where data is no longer driven. 5ns 0 to 3V 1.5V Table 5. Capacitance (1, 2) (TA = 25 C, f = 1 MHz) Symbol CIN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 7 5 Unit pF pF Note: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected. Table 6. DC Characteristics (1) (TA = 0 to 70 C; VCC = 4.5V to 5.5V) Symbol ILI (1) ILO (1) ICC VIL VIH VOL Output Low Voltage (IRQ) VOH Output High Voltage Parameter Input Leakage Current Output Leakage Current Supply Current Input Low Voltage Input High Voltage Output Low Voltage IOL = 4mA IOL = 0.5mA IOH = -1mA 2.4 Test Condition 0V VIN VCC 0V VOUT VCC Outputs open -0.3 2.2 Min Max 1 1 15 0.8 VCC + 0.3 0.4 0.4 Unit A A mA V V V V V Note: 1. Outputs deselected. 7/23 M48T86 Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C) Symbol VPFD VSO tDR (2) Parameter Power-fail Deselect Voltage Battery Back-up Switchover Voltage Expected Data Retention Time 10 Min 4.0 3.0 Typ Max 4.35 Unit V V YEARS Note: 1. All voltages referenced to VSS. 2. At 25C. Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70C) Symbol tF (1) tR tREC VCC Fall Time VCC Rise Time VPFD to E High Parameter Min 300 100 20 200 Max Unit s s ms Note: 1. VCC fall time of less than tF may result in deselection/write protection not occurring until 200s after V CC passes VPFD. Figure 7. Power Down/Up Mode AC Waveforms VCC 4.5V VPFD VSO tF tR tREC E AI01646 INTERRUPTS The RTC plus RAM includes three separate, fully automatic sources of interrupt (alarm, periodic, update-in-progress) available to a processor. The alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic interrupt can be selected from rates of 500ms to 122s. The update-ended interrupt can be used to indicate that an update cycle has completed. The processor program can select which interrupts, if any, are going to be used. Three bits in Register B enable the interrupts. Writing a logic "1" to an interrupt-enable bit (Register B; Bit 6 = PIE; Bit 5 = AIE; Bit 4 = UIE) permits an interrupt to be initialized when the event occurs. A zero in an interrupt-enable bit prohibits the IRQ pin from being asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set at an active level, although the interrupt initiating the event may have occurred much earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. 8/23 M48T86 Table 9. AC Characteristics (TA = 0 to 70 C; VCC = 4.5V to 5.5V) M48T86 Symbol tCYC tDSL tDSH tRWH tRWS tCS tCH tDHR tDHW tAS tAH tDAS tASW tASD tOD tDW tBUC tPI (1) tUC Cycle Time Pulse Width, Data Strobe Low or R/W High Pulse Width, Data Strobe High or R/W Low R/W Hold Time R/W Setup Time Chip Select Setup Time Chip Select Hold Time Read Data Hold Time Write Data Hold Time Address Setup Time Address Hold Time Delay Time, Data Strobe to Address Strobe Rise Pulse Width Address Strobe High Delay Time, Address Strobe to Data Strobe Rise Output Data Delay Time from Data Strobe Rise Write Setup Time Delay Time before Update Cycle Periodic Interrupt Time interval Time of Update Cycle - 30 244 - 1 - s Parameter Min 160 80 55 0 10 5 0 0 0 20 5 10 30 35 50 25 Typ Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s Unit Note: 1. See Table 10. When an interrupt event occurs, the related flag bit (Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is set to a logic "1". These flag bits are set independent of the state of the corresponding enable bit in Register B and can be used in a polling mode without enabling the corresponding enable bits. The interrupt flag bits are status bits which software can interrogate as necessary. When a flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read; however, care should be taken when using the flag bits as all are cleared each time Register C is read. Double latching is included with Register C so that bits which are set, remain stable throughout the read cycle. All bits which are set high are cleared when read. Any new interrupts which are pending during the read cycle are held until after the cycle is completed. One, two, or three bits can be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the corresponding enable bit is also set, the IRQ pin is asserted low. IRQ is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit (Register C; Bit 7) is a "1" whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is accomplished by reading Register C.A logic "1" in the IRQF bit indicates that one or more interrupts have been initiated by the M48T86. The act of reading Register C clears all active flag bits and the IRQF bit. 9/23 M48T86 Figure 8. Intel Bus Read Mode AC Waveforms tCYC AS tASW DS tDSL R/W tDAS E tAS AD0-AD7 tAH tDHR tCS tOD tCH tDSH tASD AI01647 Figure 9. Intel Bus Write AC Waveforms tCYC AS tDAS DS tDSL R/W tCS E tAS AD0-AD7 tAH tDW tDHW tCH tDSH tASW tASD AI01648 10/23 M48T86 Figure 10. Motorola Bus Read/Write Mode AC Waveforms AS tDAS tASW tASD tCYC DS tDSL tRWS R/W tCS E tAH tAS AD0-AD7 (Write) tAS tAH AD0-AD7 (Read) AI01649 tDSH tRWH tCH tDW tDHW tOD tDHR PERIODIC INTERRUPT The periodic interrupt will cause the IRQ pin to go to an active state from once every 500ms to once every 122s. This function is separate from the alarm interrupt which can be output from once per second to once per day. The periodic interrupt rate is selected using the same Register A bits which select the square wave frequency (see Table 10). Changing the Register A bits affects both the square wave frequency and the periodic interrupt output. However, each function has a separate enable bit in Register B. The periodic interrupt is enabled by the PIE bit (Register B; Bit 6). The periodic interrupt can be used with software counters to measure inputs, create output intervals, or await the next needed software function. ALARM INTERRUPT The alarm interrupt provides the system processor with an interrupt when a match is made between the RTC's hours, minutes, and seconds bytes and the corresponding alarm bytes. The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the Alarm Interrupt Enable bit (Register B; Bit 5) is high. The second use is to insert a "don't care" state in one or more of the three alarm bytes. The "don't care" code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the "don't care" condition when at logic "1". An alarm will be generated each hour when the "don't care" is are set in the hours byte. Similarly, an alarm is generated every minute with "don't care" codes in the hour and minute alarm bytes. The "don't care" codes in all three alarm bytes create an interrupt every second. 11/23 M48T86 Figure 11. Address Map 0 14 BYTES 13 14 CLOCK AND CONTROL STATUS REGISTERS 00 0 1 2 3 4 5 6 7 8 9 SECONDS SECONDS ALARM MINUTES MINUTES ALARM HOURS HOURS ALARM DAY OF WEEK DATE OF MONTH MONTH YEAR REGISTER A REGISTER B REGISTER C REGISTER D BCD OR BINARY FORMAT 0D 0E 114 BYTES STORAGE REGISTERS 10 11 12 13 127 7F AI01650 UPDATE CYCLE INTERRUPT After each update cycle, the update cycle ended flag bit (UF) (Register C; Bit 4) is set to a "1". If the update interrupt enable bit (UIE) (Register B; Bit 4) is set to a "1", and the SET bit (Register B; Bit 7) is a "0", then an interrupt request is generated at the end of each update cycle. SQUARE WAVE OUTPUT SELECTION Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of Figure 3. The purpose of selecting a divider tap is to generate a square wave output signal on the SQW pin. The RS3-RS0 bits in Register A establish the square wave output frequency. These frequencies are listed in Table 10. The SQW frequency selection shares the 1-of-15 selector with the periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on and off under program control with the square wave enabled (SQWE). OSCILLATOR CONTROL BITS When the M48T86 is shipped from the factory the internal oscillator is turned off. This feature prevents the lithium energy cell from being discharged until it is installed in a system. A pattern of "010" in Bits 4-6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of "11X" will turn the oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of Bits 4-6 keep the oscillator off. 12/23 M48T86 Table 10. Square Wave Frequency/Periodic Interrupt Rate Register A Bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square Wave Frequency None 256 128 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 Hz Hz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Units Periodic Interrupt Period None 3.90625 7.8125 122.070 244.141 488.281 976.5625 1.953125 3.90625 7.8125 15.625 31.25 62.5 125 250 500 ms ms us us us us ms ms ms ms ms ms ms ms ms Units UPDATE CYCLE The M48T86 executes an update cycle once per second regardless of the SET bit (Register B; Bit 7). When the SET bit is asserted, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer. This feature allows accurate time to be maintained, independent of reading and writing the time, calendar, and alarm buffers. This also guarantees that the time and calendar information will be consistent. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a "don't care" code is present in all three positions. There are three methods of accessing the real time clock that will avoid any possibility of obtaining inconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every update cycle which indicates that over 999ms are available to read valid time and date information. If this interrupt is used, the IRQF bit (Register C; Bit 7) should be cleared before leaving the interrupt routine. A second method uses the Update-In-Progress (UIP) bit (Register A; Bit 7) to determine if the update cycle is in progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs 244s later. If a low is read on the UIP bit, the user has at least 244s before the time/calendar data will be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244s. The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit is set high between the setting of the PF bit (Register C; Bit 6). Periodic interrupts that occur at a rate greater than t BUC allow valid time and date information to be reached at each occurrence of the periodic interrupt.The reads should be completed within 1/(t PL/2 + t BUC) to ensure that data is not read during the update cycle. 13/23 M48T86 Figure 12. Update Period Timing and UIP UPDATE PERIOD (1sec) UIP tBUC tUC AI01651 Figure 13. Update-ended/Periodic Interrupt Relationship UPDATE PERIOD (1sec) UIP tBUC tPI PF tPI tPI tUC UF AI01652B 14/23 M48T86 REGISTER A MSB BIT7 UIP BIT6 OSC2 BIT5 OSC1 BIT4 OSC0 BIT3 RS3 BIT2 RS2 BIT1 RS1 BIT0 RS0 UIP. Update in Progress The Update in Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is one, the update transfer will soon occur. When UIP isa zero, the update transfer will not occur for at least 244s. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is zero. The UIP bit is read only and is not affected by RST. Writing the SET bit in Register B to a "1" inhibits any update transfer and clears the UIP status bit. OSC0, OSC1, OSC2. Oscillator Control These three bits are used to control the oscillator and reset the countdown chain. A pattern of "010" enables operation by turning on the oscillator and enabling the divider chain. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When "010" is written, the first update begins after 500ms. RS3, RS2, RS1, RS0 These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected may be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user may do one of the following: 1. Enable the interrupt with the PIE bit; or 2. Enable the SQW output with the SQWE bit; or 3. Enable both at the same time and same rate; or 4. Enable neither. Table 10 lists the periodic interrupt rates and the square wave frequencies that may be chosen with the RS bits. These four read/write bits are not affected by RST. 15/23 M48T86 REGISTER B MSB BIT7 SET BIT6 PIE BIT5 AIE BIT4 UIE BIT3 SQWE BIT2 DM BIT1 24/12 BIT0 DSE SET When the SET bit is a zero, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a one, any update transfer is inhibited and the program may initialize the time and calendar bytes without an update occurring. Read cycles can be executed in a similar manner. SET is a read/write bit which is not modified by RST or internal functions of the M48T86. PIE. Periodic Interrupt Enable The Periodic Interrupt Enable bit (PIE) is a read/ write bit which allows the Periodic Interrupt Flag (PF) bit Register C to cause the IRQ pin to be driven low. When the PIE bit is set to one, periodic interrupts are generated by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A zero in the PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal M48T86 functions, but is cleared to zero on RST. AIE. Alarm Interrupt Enable The Alarm Interrupt Enable (AIE) bit is a Read/ Write bit which, when set to a one, permits the Alarm Flag (AF) bit in Register C to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes including a "don't care" alarm code of binary 1XXXXXXX. When the AIE bit is set to zero, the AF bit does not initiate the IRQ signal. The RST pin clears AIE to zero. The internal functions of the M48T86 do not affect the AIE bit. UIE. Update Ended Interrupt Enable The Update Ended Interrupt Enable (UIE) bit is a read/write bit which enables the Update End Flag (UF) bit in Register C to assert IRQ. A transition low on the RST pin or the SET bit going high clears the UIE bit. SQWE. Square Wave Enable When the Square Wave Enable (SQWE) bit is set to a one, a square wave signal is driven out on the SQW pin. The frequency is determined by the rate-selection bits RS3-RS0. When the SQWE bit is set to zero, the SQW pin is held low. The SQWE bit is cleared by the RST pin. SQWE is a read/write bit. DM. Data Mode The Data Mode (DM) bit indicates whether time and calendar information are in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is not modified by internal function or RST. A one in DM signifies binary data and a zero specifies Binary Coded Decimal (BCD) data. 24/12 The 24/12 control bit establishes the format of the hours byte.A one indicates the 24-hour mode and a zero indicates the 12-hour mode. This bit is read/ write and is not affected by internal functions or RST. DSE. Daylight Savings Enable The Daylight Savings Enable (DSE) bit is a read/ write bit which enables two special updates when set to a one. On the first Sunday in April, the time increments from 1:59:59AM to 3:00:00 AM. On the last Sunday in October, when the time reaches 1:59:59 AM, it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a zero. This bit is not affected by internal functions or RST. 16/23 M48T86 REGISTER C MSB BIT7 IRQF BIT6 PF BIT5 AF BIT4 UF BIT3 0 BIT2 0 BIT1 0 BIT0 0 IRQF. Interrupt Request Flag The Interrupt Request Flag (IRQF) bit is set to a one when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 (i.e. IRQF = PF*PIE+AF*AIE+UF*UIE) PF. Periodic Interrupt Flag The Periodic Interrupt Flag (PF) is a read-only bit which is set to a one when an edge is detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic rate. PF is set to a one independent of the state of the PIE bit. The IRQ signal is active and will set the IRQF bit. The PF bit is cleared by a RST or a software read of Register C. AF. Alarm Flag A one in the AF (Alarm Interrupt Flag) bit indicates that the current time has matched the alarm time. If the AIE bit is also a one, the IRQ pin will go low and a one will appear in the IRQF bit. A RST or a read of Register C will clear AF. UF. Update Ended Interrupt Flag The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to a one, the one in the UF bit causes the IRQF bit to be a one. This will assert the IRQ pin. UF is cleared by reading Register C or an RST. BIT 0 through 3. Unused Bits Bit 3-Bit 0 are unused. These bits always read zero and cannot be written. REGISTER D MSB BIT7 VRT BIT6 0 BIT5 0 BIT4 0 BIT3 0 BIT2 0 BIT1 0 BIT0 0 VRT. Valid Ram And Time The Valid RAM and Time (VRT) bit is set to the one state by STMicroelectronics prior to shipment. This bit is not writable and should always be a one when read. If a zero is ever present, an exhausted internal lithium cell is indicated and both the contents of the RTC data and RAM data are questionable. This bit is unaffected by RST. BIT 0 through 6. Unused Bits The remaining bits of Register D are not usable. They cannot be written and when read, they will always read zero. 17/23 M48T86 POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the V CC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 14) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below V SS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from V CC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 14. Supply Voltage Protection VCC VCC 0.1F DEVICE VSS AI02169 18/23 M48T86 Table 11. Ordering Information Scheme Example: Device Type M48T Package PC = PCDIP24 MH (1) = SOH28 Temperature Range 1 = 0 to 70 C Shipping Method for SOIC blank = Tubes TR = Tape & Reel M48T86 MH 1 TR Note: 1. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number "M4T28-BR12SH1" in plastic tube or "M4T28-BR12SH1TR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since will drain the lithium button-cell battery. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 12. Revision History Date March 1999 05/04/00 First Issue Page layout changed Revision Details 19/23 M48T86 Table 13. PCDIP24 - 24 pin Plastic DIP, battery CAPHAT, Package Mechanical Data mm Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.36 0.38 1.14 0.20 34.29 17.83 2.29 25.15 15.24 3.05 24 Max 9.65 0.76 8.89 053 1.78 0.31 34.80 18.34 2.79 30.73 16.00 3.81 Typ Min 0.3500 0.0150 0.3291 0.0150 0.0449 0.0079 1.3500 0.7020 0.0902 0.9902 0.6000 0.1201 24 Max 0.3799 0.0299 0.3500 0.0209 0.0701 0.0122 1.3701 0.7220 0.1098 1.2098 0.6299 0.1500 inches Figure 15. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline A2 A A1 B1 B e3 D N L eA C e1 E 1 PCDIP Drawing is not to scale. 20/23 M48T86 Table 14. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data mm Symb Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.0500 0.0020 0.0921 0.0142 0.0059 0.6972 0.3240 - 0.1260 0.4531 0.0161 0 28 0.0039 Typ Min Max 0.1201 0.0142 0.1059 0.0201 0.0126 0.7280 0.3500 - 0.1421 0.5000 0.0500 8 inches Figure 16. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline A2 B e A C eB CP D N E H A1 L 1 SOH-A Drawing is not to scale. 21/23 M48T86 Table 15. M4T28-BR12SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.0181 0.8350 0.5598 0.6122 0.1260 0.0799 0.2650 0.2551 Typ Min Max 0.3850 0.2850 0.2752 0.0150 0.0220 0.8598 0.5902 0.6280 0.1421 0.0902 inches Figure 17. M4T28-BR12SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline A1 A2 A A3 eA D B eB L E SH Drawing is not to scale. 22/23 M48T86 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 23/23 |
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